The present invention relates to solid state devices and to wafers upon which silicon solid state devices may be fabricated.
Silicon solid state devices such as, for example, transistors, diodes and integrated circuits are conventionally fabricated by building up the devices on the surface of a wafer. Once formed, the devices are separated into individual dice for subsequent packaging and use. Manufacturing economy is urging an increase in wafer size from the conventional 3-inch diameter to 4-inch and larger diameters. As the wafer size increases, maintaining uniformity of processing over the entire surface area of the wafer becomes more difficult. In addition, the stringency of specifications for the wafer continue to increase.
Some types of devices require a high-resistivity silicon layer a few mils thick with a closely controlled impurity level. Such a thickness makes the silicon layer too fragile for unsupported handling during processing, particularly in wafers having diameters of four inches and more. It has thus been the practice to epitaxially grow a thin high-resistivity crystalline silicon layer on a thick low-resistivity single-crystal substrate. The surface of the epitaxial layer being used for the formation of the semiconductor device. As the required resistivity and thickness of the epitaxial layer become larger, the properties of the epitaxial layer become more difficult to control to the level required in demanding applications. That is, at high resistivity and large thickness, surface faults and bulk crystalline defects multiply. This makes the epitaxial layer unsuitable in, for example, the fabrication of bipolar transistors which are capable of operating at voltages in excess of about 1000 volts.